View AN-9732_6260519.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

www.fairchildsemi.com ? 2011 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.0.0 ? 3/23/11 AN-9732 led application design guide using bcm power factor correction (pfc) controller for 200w lighting system 1. introduction this application note presents practical step-by-step design considerations for a boundary-conduction-mode (bcm) power-factor-correction (pfc) converter employing fairchild pfc controller, fl7930. it includes designing the inductor and zero-current-detection (zcd) circuit, selecting the components, and closing the control loop. the design procedure is verified through an experimental 200w prototype converter. unlike the continuous conduction mode (ccm) technique often used at this power level, bcm offers inherent zero- current switching of the boost diodes (no reverse-recovery losses), which permits the use of less expensive diodes without sacrificing efficiency. the fl3930b provides an additional ovp pin that can be used to shut down the boost power stage when output voltage exceeds ovp level due to damaged resistors connected at the inv pin. the fl7930c provides a pfc- ready pin can be used to trigger other power stages when pfc output voltage reaches the proper level (with hysteresis). this signal can be used as the v cc trigger signal for another power stage controller after pfc stage or be transferred to the secondary side to synchronize the operation with pfc voltage condition. this simplifies the external circuit around the pfc controller and saves total bom cost. the internal proprietary logic for detecting input voltage greatly improves the stability of pfc operation. together with the maximum switching frequency clamping at 300khz. fl7930 can limit inductor current within pre- designed value at one or two cycles of the ac-input-absent test to simulate a sudden blackout. due to the startup- without-overshoot design, audible noise from repetitive ovp triggering is eliminated. protection functions include output over-voltage, over-current, open-feedback, and under-voltage lockout. an excel ? -based design tool is available with this application note and the design result is shown with the calculation results as an example. figure 1. typical application circuit
AN-9732 application note ? 2011 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.0.0 ? 3/23/11 2 2. operation principle of bcm boost pfc converter the most widely used operation modes for the boost converter are continuous conduction mode (ccm) and boundary conduction mode (bcm). these two descriptive names refer to the current flowing through the energy storage inductor of the boost converter, as depicted in figure 2. as the names indicat e, the inductor current in ccm is continuous; while in bcm, the new switching period is initiated when the inductor current returns to zero, which is at the boundary of continuous conduction and discontinuous conduction operations. even though the bcm operation has higher rms current in the inductor and switching devices, it allows better switching condition for the mosfet and the diode. as shown in figure 2, the diode reverse recovery is el iminated and a fast-recovery diode is not needed. the mosfet is also turned on with zero current, which reduces the switching loss. figure 2. ccm vs. bcm control the fundamental idea of bcm pfc is that the inductor current starts from zero in ea ch switching period, as shown in figure 3. when the power transistor of the boost converter is turned on for a fixed time, the peak inductor current is proportional to the input voltage. since the current waveform is triangular; the average value in each switching period is proportional to the input voltage. in a sinusoidal input voltage, the input current of the converter follows the input voltage waveform with very high accuracy and draws a sinusoidal input current from the source. this behavior makes the boost converter in bcm operation an ideal candidate for power factor correction. a by-product of bcm is that the boost converter runs with variable switching frequency that depends primarily on the selected output voltage, the instantaneous value of the input voltage, the boost inductor value, and the output power delivered to the load. the op erating frequency changes as the input current follows the sinusoidal input voltage waveform, as shown in figure 3. the lowest frequency occurs at the peak of sinusoidal line voltage. figure 3. operation waveforms of bcm pfc the voltage-second balance equation for the inductor is: ? ? off in out on in t ) t ( v v t ) t ( v ? ? ? ? (1) where v in(t) is the rectified line voltage and v out is the output voltage. the switching frequency of bcm boost pfc converter is: ?? out line pk , in out on out in out on off on sw v t f 2 sin v v t 1 v ) t ( v v t 1 t t 1 f ? ? ? ? ? ? ? ? ? ? ? ? (2) where v in,pk is the amplitude of the line voltage and f line is the line frequency. figure 4 shows how the mosfet on time and switching frequency changes as output power decreases. when the load decreases, as shown in the right side of figure 4, the peak inductor current dimini shes with reduced mosfet on time and, therefore, the switching frequency increases. since this can cause severe switching losses at light-load condition and too-high switching frequency operation may occur at startup, the maximum switching frequency of fl7930 is limited to 300khz.
AN-9732 application note ? 2011 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.0.0 ? 3/23/11 3 figure 4. frequency variation of bcm pfc since the design of the filter and inductor for a bcm pfc converter with variable switchi ng frequency should be at minimum frequency condition, it is worthwhile to examine how the minimum frequency of bcm pfc converter changes with operating conditions. figure 5 shows the minimum switching frequency, which occurs at the peak of line voltage as a function of the rms line voltage for three output voltage settings. it is interesting that, depending on where the output voltage is set, the minimum switching frequency may occur at the minimum or at the maximum line voltage. when the output voltage is approximately 405v, the minimum switching frequency is the same for both low line (85v ac ) and high line (265v ac ). figure 5. minimum switching frequency vs. rms line voltage (l = 200h, p out = 200w) 3. startup without overshoot and ac-absent detection because feedback control speed of the pfc is typically quite slow, there is a gap between output voltage and feedback control. therefore, over-voltage protection (ovp) is critical at the pfc controller. voltage dip caused by fast load change from light to heavy is diminished by a large bulk capacitor. ovp is easily triggered at startup. switching starting and stopping by ovp at startup may cause audible noise and can increase voltage stress at startup, which may be higher than normal operation. this is improved if soft- start time is very long, but too-long start time raises the time needed for the output voltage to reach the rated value at light load. fl7930 includes a startup without overshoot feature. during startup, the feedback loop is controlled by an internal proportional gain controller and, when the output voltage reaches the vicinity of the rated value, changed to the external compensator after an internally fixed transition time described in the figure 6. in short, an internal proportional gain controller prevents overshoot at startup; external conventional compensator takes over after startup. figure 6. startup without overshoot fl7930 eliminates ac input voltage detection to save the power loss caused by an input-voltage-sensing resistor array and to optimize thd. therefore, no information about input voltage is available at the inte rnal controller. in many cases, the v cc of pfc controller is supplied by an independent power source, like standby po wer, so when the electric power is suddenly interrupted during one or two ac line periods, v cc is still alive during that time and pfc output voltage drops. accordingly, the control loop tries to compensate output voltage drop and control voltage reaches its maximum. when ac line input voltage is live, control voltage allows high switching current and creates stress on the mosfet and diode. to protect against this, fl7930 checks if the input ac voltage exists. once controller verifies that the input voltage does not exist, soft-start is reset and waits until ac input voltage is applied again. soft- start manages the turn-on time for smooth operation after detecting that the ac voltage is live and results in less voltage and current stress during startup. 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 85 130 175 220 265 minimum switching frequency[khz] line voltage [v] vout=385v vout=400v vout=415v
AN-9732 application note ? 2011 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.0.0 ? 3/23/11 4 figure 7. ac-off operation without ac-absent detection circuit figure 8. ac-off operation with ac-absent detection circuit 4. design considerations in this section, a design pr ocedure is presented using the schematic in figure 9 as a reference. a 200w pfc application with universal input range is selected as a design example. the design specifications are: ? line voltage range: 90~265v ac (universal input), 50hz ? nominal output voltage and current: 400v/0.5a (200w) ? hold-up time requirement: output voltage should not drop below 330v during one line cycle ? output voltage ripple: less than 8v pp ? minimum switching frequency: higher than 50khz ? control bandwidth: 5~15hz ? v cc supplied from auxiliary power supply. figure 9. reference circuit for design example of bcm boost pfc
AN-9732 application note ? 2011 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.0.0 ? 3/23/11 5 [step-1] define system specifications ? line frequency range ( v line,min and v line,max ) ? line frequency ( f line ) ? output-voltage ( v out ) ? output load current ( i out ) ? output power ( p out = v out ? i out ) ? estimated efficiency ( ? ) to calculate the maximum input power, it is necessary to estimate the power conversion ef ficiency. at universal input range, efficiency is recommended at 0.9; 0.93~0.95 is recommended when input voltage is high. when input voltage is set at the minimum, input current becomes the maximum to deliver the same power compared at high line. maximum boost inductor current can be detected at the minimum line voltage and at its peak. inductor current can be divided into two categories; one is rising current when mosfet is on and the other is output diode current when mosfet is off, as shown in figure 10. figure 10. inductor and input current because switching frequency is much higher than line frequency, input current can be assumed to be constant during a switching period, as shown in figure 11. figure 11. inductor and input current with the estimated efficiency, figure 10 and figure 11 inductor current peak (i l,pk ) , maximum input current (i in,max ), and input root mean square (rms) current (i in,maxrms ) are given as: ] a [ v 2 p 4 i min , line out pk , l ? ? ? ? ? (3) ] a [ 2 / i i pk , l max , in ? (4) ] a [ 2 / i i max , in maxrms , in ? (5) (design example) input voltage range is universal input, output load is 500ma, and esti mated efficiency is selected as 0.9. 9 . 0 500 , 400 50 265 , 90 , , ? ? ? ? ? ? ? ma i v v hz f v v v v out out line ac max line ac min line a a i i a a i i a a v v p i max in maxrms in pk l max in min line out pk l 469 . 2 2 492 . 3 2 492 . 3 2 984 . 6 2 984 . 6 90 2 9 . 0 5 . 0 400 4 2 4 , , , , , , ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? [step-2] boost inductor design the boost inductor value is determined by the output power and the minimum switching frequency. the minimum switching frequency must be higher than the maximum audible frequency band of 20khz. minimum frequency near 20khz can decrease switching loss with the cost of increased inductor size an d line filter size. too-high minimum frequency may increas e the switching loss and make the system respond to noise. selecting in the range of about 30~60khz is a comm on choice; 40~50khz is recommended with fl7930. the minimum switching frequency may appear at minimum input voltage or maximum input voltage, depending on the output voltage level. when pfc output voltage is less than 405v, minimum switching appears at the maximum input voltage, according to applica tion note an-6 086. inductance is obtained using the minimum switching frequency: ? ? ] h [ v 2 v v 2 1 p f 4 v 2 l line out line out min , sw 2 line ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? (6) where l is boost inductance and f sw,min is the minimum switching frequency.
AN-9732 application note ? 2011 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.0.0 ? 3/23/11 6 the maximum on time needed to carry peak inductor current is calculated as: [s] v 2 i l t min line, pk l, max on, ? ? ? (7) once inductance and the maximum inductor current are calculated, the number of turns of the boost inductor should be determined considering the core saturation. the minimum number of turns is given as: ] turns [ b ] mm [ a ] h [ l i n 2 e pk , l boost ? ? ? ? ? (8) where a e is the cross-sectional area of core and ? b is the maximum flux swing of the core in tesla. ? b should be set below the saturation flux density. figure 12 shows the typical b-h characteristic s of ferrite core from tdk (pc45). since the saturation flux density ( ? b ) decreases as the temperat ure increases, the high temperature characteristics should be considered. rms inductor current (i l,rms ) and current density of the coil (i l,density ) can be given as: ] a [ 6 i i pk , l rms , l ? (9) ] mm / a [ n 2 d i i 2 wire 2 wire rms , l density , l ? ? ? ? ? ? ? ? ? ? (10) where d wire is the diameter of winding wire and n wire is the number of strands of winding wire. when selecting wire diameter and strands; current density, window area (a w , refer to figure 13 ) of selected core, and fill factor need to be considered. winding sequence of the boost inductor is relatively simple compared to a dc-dc converter, so fill factor can be assumed about 0.2~0.3. layers cause the skin effect and proximity effect in the coil, so real current density may be higher than expected. figure 12. typical b-h curves of ferrite core figure 13. a e and a w (design example) since the output voltage is 400v, the minimum frequency occurs at high-line (265v ac ) and full- load condition. assuming the efficiency is 90% and selecting the minimum frequen cy as 50khz, the inductor value is obtained as: ? ? ?? ] [ 4 . 199 265 2 400 265 2 1 200 10 50 4 265 2 9 . 0 2 2 1 4 2 3 2 , 2 h v v v p f v l line out line out min sw line ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? assuming eer3019n core (pl-7, a e =137mm 2 ) is used and setting ? b as 0.3t, the primary winding should be: ] [ 34 3 . 0 137 284 984 . 6 ] [ ] [ 2 , t b mm a h l i n e pk l boost ? ? ? ? ? ? ? ? ? the number of turns (n boost ) of the boost inductor is determined as 34 turns. when 0.10mm diameter and 50-strand wire is used, rms current of inductor coil and current density are: ] [ 85 . 2 6 984 . 6 6 , , a i i pk l rms l ? ? ? ?? ] / [ 3 . 7 50 2 / 1 . 0 85 . 2 2 2 2 2 , , mm a n d i i wire wire rms l density l ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?
AN-9732 application note ? 2011 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.0.0 ? 3/23/11 7 [step-3] inductor auxiliary winding design figure 14 shows the application circuit of nearby zcd pin from auxiliary winding. figure 14. application circuit of zcd pin the first role of zcd winding is detecting the zero-current point of the boost inductor. once the boost inductor current becomes zero, the effectiv e capacitor shown at the mosfet drain pin (c eff ) and the boost inductor resonate together. to minimize the constant turn-on time deterioration and turn-on loss, the gate is turned on again when the drain source voltage of the mosfet (v ds ) reaches the valley point shown in figure 15. when input voltage is lower than half of the boosted output voltage, zero voltage switching (zvs) is possible if mosfet turn- on is triggered at valley point. figure 15. zcd detection waveforms auxiliary winding must give enough energy to trigger zcd threshold to detect zero current. minimum auxiliary winding turns are given as: ] turns [ v 2 v n v 5 . 1 n max , line out boost aux ? ? ? (11) where 1.5v is the positive threshold of the zcd pin. to guarantee stable operation, auxiliary winding turns are recommended to add 2~3 turns to the calculation result of equation (11) . however, too many auxiliary winding turns raise the negative clamping loss at high line and positive clamping loss at low line. (design example) 34 turns are selected as boost inductor turns and auxiliary winding turns are calculated as: ] turns [ 02 . 2 265 2 400 34 5 . 1 v 2 v n v 5 . 1 n max , line out boost aux ? ? ? ? ? ? ? ? choice should be around 4~5 turns after adding 2~3 turns. [step-4] zcd circuit design if a transition time when v auxiliary drops from 1.4v to 0v is ignored from figure 15, the needed additional delay by the external resistor and capacitor is one quarter of the resonant period. the time constant made by zcd resistor and capacitor should be the sa me as one quarter of the resonant period: 4 l c 2 c r eff zcd zcd ? ? ? ? (12) where c eff is the effective capacitor shown at the mosfet drain pin; c zcd is the external capacitance at the zcd pin; and r zcd is the external resistance at the zcd pin. the second role of r zcd is the current limit of the internal negative clamp circuit when auxiliary voltage drops to negative due to mosfet turn on. zcd voltage is clamped 0.65v and minimum r zcd can be given as: ] [ ma 3 v 65 . 0 v 2 n n r max , line boost aux zcd ? ? ? ? ? ? ? ? ? ? ? (13) where 3ma is the clamping capability of the zcd pin. the calculation result of equation (13) is normally higher than 15k ? . if 20k ? is assumed as r zcd , calculated c zcd from equation (12) is around 10pf when the other components are assumed as conventional values used in the
AN-9732 application note ? 2011 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.0.0 ? 3/23/11 8 field. because most ic pins have several pf parasitic capacitance, c zcd can be eliminated when r zcd is higher than 30k ? . however, a small capacitor would be helpful when auxiliary winding suffe rs from operating noise. the pfc control loop has two conflicting goals: output voltage regulation and making the input current shape the same as input voltage. if the control loop reacts to regulate output voltage smoothly, as shown in figure 16, control voltage varies widely with the input voltage variation. input current acts to the control loop and sinusoidal input current shape cannot be attained. this is the reason control response of most pfc topologies is very slow and turn-on time over ac period is kept constant. this is also the reason output voltage ripple is made by input and output power relationship, not by control-loop performance. v in & v out t v control i acin figure 16. input current deterioration by fast control if on-time is controlled constantly over one ac period, inductor current peak follows ac input voltage shape and achieves good power factor. off-time is basically inductor current reset time due to the boundary mode and is determined by the input and output voltage difference. when input voltage is at its peak, the voltage difference between input and output voltage is small, and long turn-off time is necessary. when input voltage is near zero, turn-off time is short, as shown in figure 17 and figure 18. though inductor current drops to zero, there is a minor delay, explained above. the delay can be assumed as fixed when ac is at line peak and zero. near ac line peak, the inductor current decreasing slope is slow and inductor current slope is also slow during the zcd delay. the amount of negative current is not much higher than the inductor current peak. near the ac line zero, induct or current decreasing slope is very high and the amount of negative current is higher than positive inductor current peak because input voltage is almost zero. figure 17. inductor current at ac voltage peak figure 18. inductor current at ac voltage zero negative inductor current create s zero current distortion and degrades the power factor. improve this by extending turn- on time at the ac line in put near the zero cross. negative auxiliary winding voltage, when mosfet is turned on, is linearly proportional to the input voltage. sourcing current generated by the internal negative clamping circuit is also proportional to sinusoidal input voltage. that current is detected internally and added to the internal sawtooth generator, as shown in figure 19.
AN-9732 application note ? 2011 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.0.0 ? 3/23/11 9 figure 19. zcd current and sawtooth generator when ac input voltage is almost zero, no negative current is generated from inside, but sourcing current when input voltage is high is used to raise the sawtooth generator slope and turn-on time is shorter. as a result, turn-on time when ac voltage is zero is longer compared to ac voltage, in peaks shown in figure 20. figure 20. thd improvement the current that comes from the zcd pin, when auxiliary voltage is negative, depends on r zcd . the second role of r zcd is also related with the improving the total harmonic distortion (thd). the third role of r zcd is making the maximum turn-on time adjustment. depending on sourcing current from the zcd pin, the maximum on-time varies as in figure 21. figure 21. maximum on-time variation vs. i zcd with the aid of i zcd , an internal sawtooth generator slope is changed and turn-on time varies as shown in figure 22. figure 22. internal sawtooth wave slope variation r zcd also influences control range. because fl7930 doesn?t detect input voltage, voltage-mode control value is determined by the turn-on time to deliver needed current to boost output voltage. when input voltage increases, control voltage decreases rapidly. fo r example, if input voltage doubles, control voltage drops to one quarter. making control voltage maximum when input voltage is low and at full load is necessary to use the whole control range for the rest of the input voltage conditions. matching maximum turn-on time needed at low line is calculated in equation (7) and turn-on time adjustment by r zcd guarantees use of the full control range. r zcd for control range optimization is obtained as: ] [ n ma 469 . 0 n v 2 t t s 28 r boost aux min , line max , on 1 max , on zcd ? ? ? ? ? ? ? ? (14) where: t on,max is calculated by equation (7); t on,max1 is maximum on-time programming 1; n boost is the winding turns of boost inductor; and n aux is the auxiliary winding turns. r zcd calculated by equation (13) is normally lower than the value calculated in equation (14) . to guarantee the needed turn on-time for the boost inductor to deliver rated power, the r zcd from equation (13) is normally not suitable. r zcd should be higher than the result of equation (14) when output voltage drops as a result of low line voltage.
AN-9732 application note ? 2011 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.0.0 ? 3/23/11 10 when input voltage is high and load is light, not much input current is needed and control voltage of v comp touches switching stop level, such as if fl7930 is 1v. however, in some applications, a pfc block is needed to operate normally at light load. to compensate control range correctly, input voltage sensing is necessary, such as with fairchild?s interleaved pfc c ontroller fan9612, or special care on sawtooth generator is necessary. without it, optimizing r zcd is only slightly helpful for control range. this is explained and depicted in the associated excel ? design tool ?comp range? worksheet. to guarantee enough control range at high line, clamping output voltage lower than rated on the minimum input condition can help. (design example) minimum r zcd for clamping capability is calculated as: ? k 2 . 18 ma 3 v 65 . 0 265 2 34 5 ma 3 v 65 . 0 v 2 n n r max , line boost aux zcd ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? minimum r zcd for control range is calculated as: ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? k 2 . 37 34 ma 469 . 0 5 90 2 s 9 . 10 s 42 s 28 n ma 469 . 0 n v 2 t t s 28 r boost aux min , line max , on 1 max , on zcd a choice close to the value calculated by the control range is recommended. 39k ? is chosen in this case. [step-5] output capacitor selection the output voltage ripple should be considered when selecting the output capacitor. figure 23 shows the line frequency ripple on the output voltage. with a given specification of output ripple, the condition for the output capacitor is obtained as: ] f [ v f 2 i c ripple , out line out out ? ? ? ? ? (15) where v out,ripple is the peak-to-peak output voltage ripple specification. the output voltage ripple caused by esr of electrolytic capacitor is not as serious as other power converters because output voltage is high and load current is small. since too much ripple on the output voltage may cause premature ovp during normal operation, the peak-to-peak ripple specification should be smalle r than 15% of the nominal output voltage. the hold-up time should also be considered when determining the output capacitor as: ?? ] f [ v v 5 . 0 v t p 2 c 2 min , out 2 ripple , out out hold out out ? ? ? ? ? ? ? (16) where t hold is the required hold-up time and v out,min is the minimum output voltage during hold-up time. t i diode i diode,ave i diode,ave =i out (1-cos(4p.f l .t)) v out i out v out,ripple = i out 2p.f l .c out figure 23. output voltage ripple the voltage rating of capacitor can be obtained as: ] v [ v v v v out ref max , p ov cout , st ? ? (17) where v ovp,max and v ref are the maximum tolerance specifications of over-voltage protection triggering voltage and reference voltage at error amplifier.
AN-9732 application note ? 2011 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.0.0 ? 3/23/11 11 (design example) with the ripple specification of 8v p-p , the capacitor should be: ] [ 9 . 198 8 50 2 5 . 0 2 , f v f i c ripple out line out o ? ? ? ? ? ? ? ? ? ? ? since minimum allowable output voltage during one cycle line (20ms) drop-outs is 330v, the capacitor should be: ?? ?? ] [ 167 330 8 5 . 0 400 10 20 200 2 5 . 0 2 2 2 3 2 , 2 , f v v v t p c min out ripple out out hold out o ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? to meet both conditions, the output capacitor must be larger than 140 ? f. a 240 ? f capacitor is selected for the outpu t capacitor. the voltage stress of selected capacitor is calculated as: ] v [ 8 . 436 400 500 . 2 730 . 2 v v v v out ref max , ovp cout , st ? ? ? ? ? [step-6] mosfet and diode selection selecting the mosfet and diode needs extensive knowledge and calculation rega rding loss mechanisms and gets more complicated if proper selection of a heatsink is added. sometimes the loss calculation itself is based on assumptions that may be far from reality. refer to industry resources regarding these topics. this note shows the voltage rating and switching loss calculations based on the linear approximation. the voltage stress of the mosfet is obtained as: ] v [ v v v v v dout , drop out ref max , p ov q , st ? ? ? (18) where v drop,dout is the maximum forward-voltage drop of output diode. after the mosfet is turned off, the output diode turns on and a large output electrolytic capacitor is shown at the drain pin, thus a drain voltag e clamping circuit that is necessary on other topologies is not necessary in pfc. during the turn-off transient, boost inductor current changes the path from mosfet to output diode and before the output diode turns on; a minor voltage peak can be shown at drain pin, which is proportional to mosfet turn-off speed. mosfet loss can be divided into three parts: conduction loss, turn-off loss, and discharge loss. boundary mode guarantees zero current switching (zcs) of mosfet when turned on, so turn-on loss is negligible. the mosfet rms current and conduction loss are obtained as: ] a [ v 9 v 2 4 6 1 i i out line pk , l rms , q ? ? ? ? ? ? (19) ? ? ] [ , 2 , , w r i p on ds rms q con q ? ? (20) where i q,rms is the rms value of mosfet current, p q,con is the conduction loss caused by mosfet current, and r ds,on is the on resistance of the mosfet. on resistance is described as ?static on resistance? and varies depending on junction temperature. that variation information is normally supplied as a graph in the datasheet and may vary by manufacturer. when calculating conduction loss, generally multiply three with the r ds,on for more accurate estimation. the precise turn-off loss calcula tion is difficult because of the nonlinear characteristics of mosfet turn off. when piecewise linear current and voltage of mosfet during turn-off and inductive load are assumed, mosfet turn-off loss is obtained as: ] w [ f t i v 2 1 p sw off l out swoff , q ? ? ? ? ? (21) where t off is the turn-off time and f sw is the switching frequency. boundary mode pfc inductor current and switching frequency vary at every switching moment. rms inductor current and average switching frequency over one ac period can be used instead of instantaneous values. individual loss portions are changed according to the input voltage; maximum conduction loss appears at low line because of high input curr ent; and maximum switching off loss appears at high line because of the high switching frequency. thus, resulting loss is always lower than the summation of the two losses calculated above. capacitive discharge loss made by effective capacitance shown at drain and source, which includes mosfet c oss , an externally added capacitor to reduce dv/dt and parasitic capacitors shown at drain pin, is also dissipated at mosfet. that loss is calculated as: ?? ] w [ f v c c c 2 1 p sw 2 out par ext oss dischg , q ? ? ? ? ? (22) where: c oss is the output capacitance of mosfet; c ext is an externally added capacitor at drain and source of
AN-9732 application note ? 2011 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.0.0 ? 3/23/11 12 mosfet; and c par is the parasitic capacitance shown at drain pin. because the c oss is a function of the drain and source voltage, it is necessary to refer to graph data showing the relationship between c oss and voltage. estimate the total power dissipation of mosfet as the sum of three losses: ] w [ p p p p dischg , q swoff , q con , q q ? ? ? (23) diode voltage stress is the same as the output capacitor stress calculated in equation (17) . the average diode current and power loss are obtained as: ] a [ i i out ave , dout ? ? (24) ] w [ i v p ave , dout dout , drop dout ? ? (25) where v drop,dout is the forward voltage drop of diode. (design example) internal reference at the feedback pin is 2.5v and maximum tolerance of ovp trigger voltage is 2.730v. if fairchild?s fdp22n50n mosfet and ffpf08h60s diode are selected, v d,for is 2.1v at 8a, 25 o c, maximum r ds,on is 0.185 ? at drain current is 11a, and maximum c oss is 50pf at drain-source voltage is 480v. ] v [ 9 . 438 1 . 2 400 50 . 2 73 . 2 v v v v v diod e , drop out ref max , p ov q , st ? ? ? ? ? ? ? ?? ?? ] [ 29 . 3 3 185 . 0 400 9 90 2 4 6 1 984 . 6 9 2 4 6 1 2 , 2 , , w r v v i p on ds out line pk l con q ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ] [ 54 . 1 ) 8 . 0 / 50 ( 50 469 . 2 400 2 1 2 1 , w k ns f t i v p sw off l out swoff q ? ? ? ? ? ? ? ? ? ? ? ?? ] [ 25 . 0 ) 8 . 0 / 50 ( 400 50 2 1 2 1 2 2 , w k p f v c c c p sw out par ext oss dischg q ? ? ? ? ? ? ? ? ? ? ? diode average current and fo rward-voltage drop loss as: ] a [ 56 . 0 9 . 0 5 . 0 i i out ave , dout ? ? ? ? ] w [ 46 . 1 56 . 0 1 . 2 i v p ave , dout for , dout loss , dout ? ? ? ? ? [step-8] determine current-sense resistor it is typical to set pulse-by-pulse current limit level a little higher than the maximum indu ctor current calculated by equation (3) . for 10% margin, the current-sensing resistor is selected as: ] [ 1 . 1 i v r pk , l lim , cs cs ? ? ? (26) once resistance is calculated, its power loss at low line is calculated as: ] w [ r i p cs 2 rms , q rcs ? ? (27) power rating of the sensing resistor is recommended a twice the power rating calculated in equation (27) . (design example) maximum inductor current is 4.889a and sensing resistor is calculated as: ] [ 104 . 0 1 . 1 984 . 6 8 . 0 1 . 1 i v r pk ind lim , cs cs ? ? ? ? ? ? choosing 0.1 ? as r cs , power loss is calculated as: ] w [ 59 . 0 1 . 0 436 . 2 r i p 2 cs 2 rms , q loss , rcs ? ? ? ? ? recommended power rating of sensing resistor is 1.19w.
AN-9732 application note ? 2011 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.0.0 ? 3/23/11 13 [step-9] design compensation network the boost pfc power stage can be modeled as shown in figure 24. mosfet and diode can be changed to loss-free resistor model and then be modeled as a voltage-controlled current source supplying rc network. figure 24. small signal modeling of the power stage by averaging the diode curren t during the half line cycle, the low-frequency behavior of the voltage controlled current source of figure 24 is obtained as: ] a [ l v 2 v 4 v 2 k i line ut o line saw ave , dout ? ? ? (28) where: l is the boost inductance, v out is the output voltage; and k saw is the internal gain of sawtooth generator (that of fl7930 is 8.496 ? 10 -6 ). then the low-frequency, small-signal, control-to-output transfer function is obtained as: ?? p ut o l 2 line saw comp out f 2 s 1 1 l v 4 r v k v v ? ? ? ? ? ? ? ? (29) where out l p c r 2 2 f ? ? ? and r l is the output load resistance in a given load condition. figure 25 and figure 26 show the variation of the control- to-output transfer function for different input voltages and different loads. since dc gain and crossover frequency increase as input voltage increases, and dc gain increases as load decreases, high input voltage and light load is the worst condition for feedback loop design. figure 25. control-to-output transfer function for different input voltages figure 26. control-to-output transfer function for different loads proportional and integration (pi) control with high- frequency pole is typically used for compensation, as shown in figure 27. the compensation zero (f cz ) introduces phase boost, while the high-frequency compensation pole (f cp ) attenuates the switching ripple. the transfer function of the compensation network is obtained as: cp cz i out comp f 2 s 1 f 2 s 1 s f 2 v v ? ? ? ? ? ? ? ? ? where ?? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? hf , comp lf , comp hf , comp lf , comp comp cp lf , comp comp cz hf , comp lf , comp out i c c c c r 2 1 f c r 2 1 f c c 2 mho 115 v 5 . 2 f ? ? ? ? (30) if c comp,lf is much larger than c comp,hf , f i and f cp can be simplified as:
AN-9732 application note ? 2011 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.0.0 ? 3/23/11 14 ] hz [ c r 2 1 f ] hz [ c 2 mho 115 v 5 . 2 f hf , comp comp cp lf , comp out i ? ? ? ? ? ? ? ? ? (31) mho 115 g m ? ? figure 27. compensation network the feedback resistor is chosen to scale down the output voltage to meet the internal reference voltage: v 5 . 2 v r r r out 2 fb 1 fb 1 fb ? ? ? (32) typically, high r fb1 is used to reduce power consumption and, at the same time, c fb can be added to raise the noise immunity. the maximum c fb currently used is several nano farads. adding a capacitor at the feedback loop introduces a pole as: ?? ] hz [ c r 2 1 c r // r 2 1 f fb 2 fb fb 2 fb 1 fb fp ? ? ? ? ? ? ? ? (33) where ?? 2 fb 1 fb 2 fb 1 fb 2 fb 1 fb r r r r r // r ? ? ? though r fb1 is high, pole frequency made by the synthesized total resistance and several nano farads is several kilo hertz and rarely affects control-loop response. the procedure to design the feedback loop is: a. determine the crossover frequency (f c ) around 1/10~1/5 of line frequency. since the control-to- output transfer function of the power stage has -20db/dec slope and -90 o phase at the crossover frequency, as shown in figure 28; it is required to place the zero of the compensation network (f cz ) around the crossover frequency so 45 ? phase margin is obtained. the capacitor c comp,lf is determined as: ? ? ?? ] f [ f 2 c l v 2 mho 115 5 . 2 v k c 2 c out 2 out 2 line saw lf , comp ? ? ? ? ? ? ? (34) to place the compensation zero at the crossover frequency, the compensation resistor is obtained as: ] [ c f 2 1 r lf , comp c comp ? ? ? ? ? (35) b. place this compensator high-frequency pole (f cp ) at least a decade higher than f c to ensure that it does not interfere with the phase margin of the voltage regulation loop at its crossover frequency. it should also be sufficiently lower than the switching frequency of the converter for noise to be effectively attenuated. the capacitor c comp,hf is determined as: ] [ r f 2 1 c comp cp hf , comp ? ? ? ? ? (36) figure 28. compensation network design
AN-9732 application note ? 2011 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.0.0 ? 3/23/11 15 (design example) ifr fb1 is 11.7m ? , then r fb2 is: ? ? ? ? ? ? ? k r v v v r fb out fb 58 . 73 10 7 . 11 5 . 2 400 5 . 2 5 . 2 5 . 2 6 1 2 choosing the crossover frequency (control bandwidth) at 15hz, c comp,lf is obtained as: ?? ?? ?? ?? nf f c l v mho v k c c out out line saw lf comp 13 . 950 15 2 10 240 10 199 400 2 10 115 5 . 2 230 10 496 . 8 2 2 115 5 . 2 2 6 6 2 6 2 6 2 2 2 , ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? actual c comp,lf is determined as 1000nf since it is the closest value among the off-the-shelf capacitors. r comp is obtained as: ? ? ? ? ? ? ? ? ? ? k c f r lf comp c comp 17 . 11 10 1 . 950 15 2 1 2 1 9 , ? ? selecting the high-frequen cy pole as 150hz, c comp,hf is obtained as: nf r f c comp cp hf comp 01 . 95 10 17 . 11 150 2 1 2 1 3 , ? ? ? ? ? ? ? ? ? ? these components result in a control loop with a bandwidth of 19.5hz and phase margin of 45.6 ? . the actual bandwidth is a little larger than the asymptotic design. [step-10] line filter capacitor selection it is typical to use small bypass capacitors across the bridge rectifier output stage to filter the switching current ripple, as shown in figure 29. since the impedance of the line filter inductor at line frequency is negligible compared to the impedance of the capacitors, the line frequency behavior of the line filter stage can be mode led, as shown in figure 29. even though the bypass capacitors absorb switching ripple current, they also generate circulating capacitor current, which leads the line voltage by 90 o , as shown in figure 30. the circulating curren t through the capacitor is added to the load current and generate s displacement between line voltage and current. the displacement angle is given by: ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? out eq line 2 line 1 p c f 2 v tan ? ? ? (37) where c eq is the equivalent capacitance that appears across the ac line (c eq =c f1 +c f2 +c hf ). the resultant displacement factor is: ? ? ? cos df ? (38) since the displacement factor is related to power factor, the capacitors in the line filter stage should be selected carefully. with a given minimum displacement factor (df min ) at full-load condition, the allowable effective input capacitance is obtained as: ?? ?? ?? ] f [ df cos tan f 2 v p c mn 1 line 2 line out ea ? ? ? ? ? ? ? ? (39) one way to determine if the input capacitor is too high or pfc control routine has problems is to check power factor (pf) and total harmonic distortion (thd). pf is the degree to which input energy is effec tively transferred to the load by the multiplication of displacement factor and thd that is input current shape deterioration ratio. pfc control loop rarely has no relation to displacement factor and input capacitor rarely has no impact on the input current shape. if pf is low (high is preferable), but thd is quite good (low is preferable), it can be concluded that input capacitance is too high and pfc controller is fine. (design example) assuming the minimum displacement factor at full load is 0.98, th e equivalent input capacitance is obtained as: ?? ?? ? ? ?? ?? ?? f df f v p c mn line line out ea ? ? ? ? 0453 . 2 98 . 0 cos tan 50 2 264 9 . 0 200 cos tan 2 1 2 1 2 ? ? ? ? ? ? ? ? ? ? ? ? ? thus, the sum of the capacitors on the input side should be smaller than 2.0f.
AN-9732 application note ? 2011 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.0.0 ? 3/23/11 16 figure 29. equivalent circuit of line filter stage ? figure 30. line current displacement
AN-9732 application note ? 2011 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.0.0 ? 3/23/11 17 appendix 1: use of the rdy pin for fl7930c typically, boosted output voltage from the pfc block is used as input voltage to the dc-dc conversion block. for some types of dc-dc converter, it is recommended to trigger operation after the input voltage raised to some level. for example, llc resonant converter or forward converter?s input voltage is limited to some range to enhance performance or guarantee the stable operation. the fl7930c provides a pfc-ready pin that can be used to trigger other power stage when pfc output voltage reaches the proper level. for that purpose, the pfc rdy pin is assigned and can be used as a acknowledge signal for the dc-dc conversion stages. when pfc output voltage rises higher than the internal threshold, pfc rdy output is pulled high by the external pull-up voltage and drops to zero with hysteresis. ] v [ v v 500 . 2 v 640 . 1 v ] v [ v v 500 . 2 v 240 . 2 v out rdyl , out out rdyh , out ? ? (40) where v out,rdyh is the v out voltage to trigger pfc rdy output to pull high and v out,rdyl is the v out voltage to trigger pfc ready output to drop to zero. if rated v out is 400v dc , then v out,rdyh is 358v dc , and v out,rdyl is 262v dc . when llc resonant converter is assumed to connect at the pfc output, the rdy pin can control the v cc for the llc controller, as shown in figure 31. figure 31. rdy application circuit for v cc driving r pullup is chosen based on the current capability of internal open-drain mosfet and can be obtained as: ] [ i v v r sk , rdy sat , rdy pullup pullup ? ? ? (41) where v pullup is the pull-up voltage, v rdy,sat is the saturation voltage of the internal mosfet, and i rdy,sk is the allowable sink current for the internal mosfet. a fast diode, such as 1n4148, is needed to prohibit the emitter-base breakdown. without that diode, when rdy voltage drops to v rdy,sat after being pulled up, emitter voltage maintains operating voltage for llc controller and almost all the voltage is applied to the emitter and base. breakdown current flows from emitter, base, and drain of the mosfet to the source of mosfet. because a large electrolytic capacitor is typically used at the v cc supply, that breakdown current flows hi gh for a long time. in this case, the internal mosfet may be damaged since the external small-signal bipolar junction transistor current capability is higher than the internal rdy mosfet. once circuit configuration is settled, voltage after subtracting forward-voltage drop of the diode and voltage drop (by the multiplication of base current and r pullup ) from the v cc of fl7930c is available for the llc controller?s v cc source. another example is using rdy when the secondary side needs pfc voltage information. when a cold cathode fluorescent lamp (ccfl) is used for the backlight source of an lcd tv, the inverter stage to ignite ccfl can receive pfc output voltage dir ectly. for that application, figure 32 can be a suitable circuit configuration. figure 32. rdy application circuit using opto-coupler with this application circuit, the minimum r pullup is given by equation (42) and the maximum r pullup is limited by sufficient current to guarantee stable operation of the opto- coupler. assuming 1ma is the typical quantity to drive opto-coupler, the maximum r pullup is: ] [ ma 1 v v r f , opto pullup pullup ? ? ? (42) where v opto,r is the input forward-voltage drop of the opto- coupler. it may possible that a secondary microcontroller has authority to give a trigger signal to the ccfl inverter controller; however, after co mbining the microcontroller signal and rdy signal from the primary-side, the inverter stage is triggered only when the two signals meet the requirements at the same time.
AN-9732 application note ? 2011 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.0.0 ? 3/23/11 18 appendix 2: gate driver design fl7930 directly drives the gate of the mosfet and various combinations of gate driver circuits are possible. figure 33 and figure 31 show the three circ uits that are widely used. when only one resistor is used, the turn-on and turn-off paths follow the same routine and turn-on and turn-off speed cannot be changed simultaneously. to cover this, make different paths by two resistors and diode if possible. turn- off current flows through the diode first, instead of r on , and then r on and r off show together. accordingly, faster turn off is possible. however, turn-off path using internal gate driver?s sinking path and current is limited by sinking current capability. if a pnp transistor is added between the gate and source of the mosfet, the gate is shorted to source locally without sharing the current path to the gate driver. this makes the gate discharge to the much smaller path than that made by the controller. the possibility of ground bounce is reduced and power dissipation in the gate driver is reduced. due to new high-speed mosfet types such as supremos ? or superfet ? , gate speed is getting fast. this decreases the switching loss of the mosfet. at the same time, power systems suffer from the emi deterioration or noise problems, like gate oscillation. therefore, sometimes a gate discharge circuit is inevitable to use high-speed characteristics fully. figure 33. equivalent circuit of line filter stage the most difficult and uncertain ta sk in direct gate drive is optimizing circuit layout. gate driving path from the out pin, resistor, mosfet gate, and mosfet source to the gnd pin should be as short as possible to reduce parasitic inductance; which may make mosfet on/off speed slow or introduce unwanted gate oscillation. using a wider pcb pattern for this lane reduces parasitic inductance. to damp unwanted gate oscillation made by the capacitance at the gate pin and parasitic inductance formed by mosfet internal bonding wire and pcb pattern, proper resistance can match the impedance at the resonant frequency. to meet emi regulations or for the redundant system, fast gate speed can be sacrificed by increasing serial resistance between the gate driver and gate. an optimal gate driver circuit needs intensive knowledge of mosfet turn-on/off characteristics and consideration of the other critical performance requirements of the system. this is beyond the scope of this paper and many reference papers can be found in the industry literature.
AN-9732 application note ? 2011 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.0.0 ? 3/23/11 19 appendix 3: experimental verification to show the validity of the design procedure presented in this application note, the converter of the design example was built and tested. all the circuit components are exactly as designed in the example. figure 34 and figure 35 show the inductor current and input current for 115vac and 230vac condition. figure 36 shows the startup performance for 95v ac full-load condition. figure 37 (a) and (b) show the pfc output voltage changed under about 50v when ac input voltage was step changed from 115v to 235v and from 235v to 115v at full load. figure 38 (a) and (b) shows the pfc output voltage changed about 50v when output load was step changed from no-load to full-load condition and from full-load to no-load at 235v. the power factor at full load is 0.988 and 0.968 for 110v ac and 230v ac , respectively. figure 34. inductor curr ent waveforms at 115v ac figure 35. inductor curr ent waveforms at 230v ac figure 36. startup performance at 95v ac , full load (a) input voltage change from 115v to 235v (b) input voltage change from 235v to 115v figure 37. output dynamic response at p o =100w (a) output load change from 0w to 160w (b) output load change from 160w to 0w figure 38. output dynamic response at v in =235v ac
AN-9732 application note ? 2011 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.0.0 ? 3/23/11 20 definition of terms ? is the efficiency. ? is the displacement angle. ? b is the maximum flux swing of the core at nominal output power in tesla. a e is the cross-sectional area of core. a w is the window area of core. b max is the maximum flux density of boost inductor at maximum output power in tesla. c comp,hf is the high-frequency co mpensation capacitance. c comp,lf is the low-frequency compensation capacitance. c eff is the effective capacitance s hown at the mosfet drain pin. c ea is the effective input capacitance to meet a given displacement factor. c ext is the external capacitance at drai n-source to decrease the turn-off slope. c eq is the equivalent input capacitance. c fb is the feedback capacitance parallel with r fb2 . c out is the output capacitance. c oss is the output capacitance of power mosfet. c par is the parasitic capacitance at drain-source of power mosfet. c zcd is the capacitance connected at zcd pin to improve noise immunity. d wire is the diameter of boost inductor winding wire. df is the displacement factor between input voltage and input current. f c is the crossover frequency. f cp is the high-frequency compensation pole to attenuate the switching ripple. f cz is the compensation zero. f line is the line frequency. f i is the integral gain of the compensator. f p is the pole frequency in the pfc power stage transfer function. f sw is the switching frequency. f sw,min is the minimum switching frequency. i cs,lim is the pulse-by-pulse current limit level determined by sensing resistor. i dout,ave is the average current of output diode. i in,max is the maximum input current from the ac outlet. i in,maxrms is the maximum rms (root mean square) input current from the ac outlet. i l is the inductor current at the nominal output power. i l,pk is the maximum peak inductor cu rrent at the nominal output power. i l,rms is the rms value of the inductor current at the nominal output power. i l,density is the current density of the boost inductor coil. i out is the nominal output current of the boost pfc stage. i q,rms is the rms current at the power switch. i rdy,sk is the allowable sink current for the internal mosfet in rdy pin. k saw is the internal gain of sawtooth generator (that of fl7930 is 8.496 ? 10 -6 ). l is the boost inductance. n aux is the number of turns of auxiliary winding in boost inductor. n boost is the number of turns of primary winding in boost inductor. n wire is the number of strands of boost inductor winding wire. p dout is the loss of output diode. p out is the nominal output power of boost pfc stage. p q,con is conduction loss of the power mosfet. p q,swoff is turn-off loss of power mosfet. p q,dischrge is the drain-source capacitance discha rge loss and consumed at power mosfet. p q is the total loss of power mosfet made by p q,con , p q,swoff , and p q,discharge . p rcs is the power loss caused by current-sense resistance. r comp is the compensation resistance. r cs is the power mosfet current-sense resistance. r ds,on is the static drain-source on resistance of the power switch. r fb1 is the feedback resistance between the inv pin and output voltage.
AN-9732 application note ? 2011 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.0.0 ? 3/23/11 21 r fb2 is the feedback resistance between the inv pin and ground. r l is the output load resistance in a given load condition. r pullup is the pull-up resistance between the rdy pin and pull-up voltage. r zcd is the resistor connected at the zcd pin to optimize thd. t hold is the required hold-up time. t off is the inductor current reset time. t on,max is the maximum on time fixed internally. t on,max1 is the programmed maximum on time. v comp is compensation pin voltage. v cs,lim is power mosfet current-sense limit voltage. v drop,dout is the forward-voltage drop of output diode. v in (t) is the rectified line voltage. v in,pk is the amplitude of line voltage. v line is rms line voltage. v line,max is the maximum rms line voltage. v line,min is the minimum rms line voltage. v line,ovp is the line ovp trip point in rms. v opto,f is the input forward voltage drop of opto-coupler. v out is the pfc output voltage. v out,min is the allowable minimum output voltage during the hold-up time. v out,rdyh is the v out to trigger pfc rdy out pulls high. v out,rdyl is the v out to trigger pfc rdy out drops to zero. ? v out,ripple is the peak-to-peak output voltage ripple. v pullup is the pull-up voltage for rdy pin. v rdy,sat is the internal saturation voltage of rdy pin. v ref is the internal reference voltage for the feedback input. v ovp,max is the maximum tolerance of ov er-voltage protection specification v st,cout is the voltage stress at the output capacitor. v st,q is the voltage stress at the power mosfet.
AN-9732 application note ? 2011 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.0.0 ? 3/23/11 22 references [1] fairchild datasheet fan9612, interleaved dual bcm, pfc controller [2] fairchild datasheet fl7930 critical conduction mode pfc controller [3] fairchild application note an-6027, design of power factor correction circuit using fan7530 [4] fairchild application note an-8035, design of power factor correction circuit using fan7930 [5] fairchild application note an-6086, design consideration for interleaved bcm pfc using fan9612 [6] robert w. erikson, dragan maksimovic, fundamentals of power electronics, second edition , kluwer academic publishers, 2001. related datasheets fl7930 ? critical conduction mode pfc controller fan9611 / fan9612 ? interleaved dual bcm pfc controllers 1n/fdll 914/a/b / 916/a/b / 4148 / 4448 small signal diode pn2222a/mmbt2222a/pzt2222a npn general purpose amplifier fdp22n50n ? 600v n-channel mosfet, unifet tm ffpf08h60s ? 8a, 600v hy perfast rectifier disclaimer fairchild semiconductor reserves the right to make changes without further notice to any products herein to improve reliability, function, or design. fai rchild does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights, nor the rights of others. life support policy fairchild?s products are not authorized for use as criti cal components in life support devices or systems without the express written approval of the president of fairchild semiconductor corporation. as used herein: 1. life support devices or system s are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.

▲Up To Search▲

Price & Availability of AN-9732

	To Download AN-9732 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .